Technology and Engineering · High school

Processor, memory and cache

Run a small program step by step and see how long the processor waits for data from the cache and from memory.

In the learning section below the figure, predict, try, complete the tasks and check yourself with short questions.

Fig. 1Processor, memory and cache

Step through or play; change the cache, the numbers and the delays

Ready. Start with “Step” or “Play”.

Program

Instruction 0 of 28

0MOV R1, 0R1 ← 0 (reset the sum)
1LOAD R2, [0]R2 ← memory[0] (7)
2ADD R1, R2R1 ← R1 + R2
3LOAD R2, [1]R2 ← memory[1] (3)
4ADD R1, R2R1 ← R1 + R2
5LOAD R2, [2]R2 ← memory[2] (5)
6ADD R1, R2R1 ← R1 + R2

Clock ticks

≈ 0 ns at 3 GHz

Hits: 0
Misses: 0
R1: —

Waiting (cycles)

Cache0
RAM0
Disk0

expected sum 17

Access pattern

Learn

Progress is kept on this page only; no points are given.

1Predict
2Try
3Explain

The program adds a list of 4 numbers over 3 passes, always in the same order. With 4 cache slots it gets 8 hits. If you cut the cache to 2 slots, how many hits will there be?

Gold cartridge: the number being carried (its value on top; drawers show their address)Purple outline: a cache slot; red is a miss, green a hitThe numbers come from a single model: a simple processor without a pipeline, 1 clock tick per phase. The cache is fully associative, evicts the least recently used number and holds one number per slot; memory is loaded from disk into RAM once, in pages of 4 cells. The default delays (cache ≈ 4, RAM ≈ 200, SSD ≈ 50,000 cycles, roughly 1 ns, 70 ns and 17 µs at 3 GHz) are widely quoted orders of magnitude; real values depend on the hardware. The wagon’s travel time is not to scale; the waiting counter advances correctly in cycles. Instructions are assumed to come from a separate instruction cache.

How does a computer get a job done? Processor, memory and cacheRead the article